1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and also to a semiconductor device.
2. Description of the Related Art
The demand for miniaturization of individual semiconductor devices and large-scale integration of such devices has been and still is increasing to realize high-speed operation and also to attain versatile functionality of semiconductor circuits. However, for successful shrinkage of the device dimensions, various related difficulties are to be overcome. Such difficulties will be understood when considering miniaturization of a MOSFET which comprises an integral part of a semiconductor circuit.
For instance, with reduction of a channel length (i.e., length of the gate electrode) of the MOSFET, its threshold voltage decreases (i.e., short channel effect). If the threshold voltage decreases from an intended value, the MOSFET will operate in an unexpected way and may impair the entire function of the circuit. Moreover, the extent of the voltage drop depends sharply on the physical length of the gate electrode. It entails that, for fabrication of small dimension MOSFET's, a minor variation of the gate length originated from a process fluctuation of gate electrode formation will result in a large deviation of the threshold voltage. This short channel effect becomes especially problematic when a circuit requires a large number of MOSFET's with an identical function (such as dynamic random memories, DRAM). The strict requirements for the functional uniformity of the individual device can be satisfied only through an extremely tight quality control of the manufacturing processes, thus restricting the manufacturability of integrated circuits such as DRAMs.
The short channel effect is caused when distortion of electric field in the vicinity of the source and drain electrodes comes to influence the electric field around the center of the channel with the reduction of the channel length. The influence can be avoided by bringing the pn junction formed by the source and the drain closer to the semiconductor surface (i.e., by making the source and drain shallower). However, when the source and drain are simply made shallow, the electric resistance of the source and electrodes increases and obstructs high speed transmission of signals through the device.
To counter this problem, it is a common practice that upper portions of the source and drain regions are chemically combined with a metal to produce a compound (silicidation) which shows significantly lower resistivity than silicon. Metals that can be used for silicidation include Co, Ti and Ni, of which Co is most suitable. This is because it does not show any rise in the electric resistance when it is formed on thin lines (i.e., lack of narrow line effects) and is stable at high temperature. These preferable characteristics of the Co silicidation stand LSI fabrication in good stead.
However, during the silicidation reaction, metal atoms quickly diffuse into the silicon substrate and eventually penetrate the junctions forming the source and drain electrodes if the source and drain are made shallow. When the metal atoms migrate beyond the junctions of the source and drain, they generate leakage currents through the junctions. And source and drain electrodes stop functioning properly.
In fact, the metal atoms diffuse very quickly. In the case of Co, the Co atoms reach a depth of 150 nm even during the silicidation process at 800° C. for 30 seconds. FIG. 6 shows leakage levels of n+/p junctions with 35 nm-thick CoSi2 layer thereon as a function of the junction depth (the depth includes the 35 nm of the silicide layer thickness). For reference, leakage levels of silicide-less junctions are also plotted. From FIG. 6, a sizable increase of the leakage current is already evidenced at the depth of 150 nm from the surface, which is by far deeper than the bottom of the silicide film. The increase is due to a rapid migration of the Co atoms into the silicon substrate. In general, rapid diffusion of metal atoms proceeds inevitably along the interfaces between metal and silicon during the silicidation reaction. The metal atoms that have penetrated deep into the silicon substrate form generation-recombination centers in the band gap of silicon and mediate junction leakage currents. If such gap states are formed in the source/drain junctions, leak currents flow through the source/drain electrodes towards the silicon substrate. Then, the function of the MOSFET is impaired. When the MOSFET constitutes a part of a DRAM's memory cell, the data stored in the cell will be lost and the semiconductor circuit will no longer operate properly.
To alleviate this problem, a technique (known as elevated source/drain method) for selective formation of additional silicon layers on the source and drain regions are developed. With this technique, the surfaces of the semiconductor substrate, where the source and drain electrodes are to be formed, are raised above the original semiconductor surface (where the channel is formed). Then, over the additionally elevated surfaces, pn junction formation for the source and drain regions and the silicidation process are performed. The junctions formed in this way can be located at a shallow position relative to the original surface of the semiconductor substrate, while maintaining a deep position as viewed from the newly elevated surfaces of source and drain regions. Hence, a sufficient thickness of the source/drain electrodes can be secured.
Such a selective elevation of source and drain surfaces can be realized by using a technique known as selective epitaxial growth. However, for this technique to be successfully applied to actual device fabrication, the final position of the resulting pn junction of the source/drain regions needs to be precisely positioned at the original semiconductor surface (where the channel is formed) or be located slightly below it. This is because drivability of the MOSFET is remarkably reduced if the junction is located above the original surface (the channel interface), whereas a severe short channel effect appears if the junctions are located far below the original surface.
However, the epitaxial growth is very sensitive to the state of the substrate surface on which the selective silicon growth is to be achieved. For instance, the thickness of the silicon film grown on the substrate varies depending on the roughness or crystalline structure of the substrate surface. Also, the quality of the grown film (i.e., the presence/absence of the crystalline defects in the film) depends on the surface condition of the substrate. Thus, for example, incomplete removal of a native oxide on the substrate surface or residual process-damage incurred during gate electrode formation may well result in severe variation in the film thickness between individual devices for which elevation of source and drain regions is attempted.
If the thickness of the additionally formed silicon films is not uniform, it is very difficult to place pn junctions of source/drain regions near the original surface of the semiconductor substrate (where the channel is formed) in a controlled manner. Impurities for the source/drain formation are introduced through the surfaces of the additionally formed silicon films. Non-uniform thickness of the additionally formed silicon films makes the relative distances from their surfaces to the original semiconductor surface (i.e., channel surface) indefinite. Thus, the junctions cannot be accurately placed at the original semiconductor surface whose location is indefinite relative to the surfaces from where the impurities are introduced.
Likewise, if the quality of the grown silicon films differs from a device to a device, it becomes difficult to place the pn junctions precisely at the targeted position near the original semiconductor surface. This is because, the presence of crystal defects in the film (i.e., the film quality) greatly influences the speed of impurity diffusion in the film (e.g., transient enhanced diffusion). It entails that a predetermined thermal diffusion of the impurity for the junction formation could result in non-uniform junction depth due to unexpected impurity diffusion caused by the crystal defects in the film.
Similarly, the diffusion of metal atoms during silicidation is also subject to the quality of the grown silicon films. Thus, even when the source and drain regions are raised by the additional silicon films, if their thickness and quality are non-uniform, metal atoms can easily diffuse and penetrate the junctions at points where the film thickness is thin or the film quality is low. It follows that the non-uniformity of the film thickness and quality limits the effectiveness of the epitaxial growth to counter the leakage generation by the silicidation process.
Furthermore, the metal diffusion in a silicon crystal is very fast itself. Accordingly, in order to block the metal diffusion effectively, the additional silicon layer must be very thick (i.e., thicker than 150 nm). However, due to above-describe reasons, it is almost impossible to selectively and uniformly grow silicon layers as thick as 150 nm on the individual source and drain regions.
Moreover, the height of the source and drain regions, raised by 150 nm, almost equals the height of the gate electrodes. The lack of the height-difference makes it difficult to ensure electrical isolation between gate electrodes and source/drain regions when silicidation process is applied to these electrodes and regions simultaneously (SALICIDE (self-align-silicide) process).
In addition, a selectively grown silicon film tends to become thinner in a region adjacent to a gate electrode (which is an intrinsic characteristic of the epitaxial growth). Prior to the silicidation process, the shortest distance between a metal film deposited on the device surface and the source/drain junction is determined at this portion. Hence it is this thinner region that could eventually limit the film's ability to block the metal diffusion regardless of the thickness of the additional silicon films grown elsewhere.
As described above, in manufacturing of a small-dimension MOSFET device, a silicide layer must be formed on source and drain regions to secure low electrical resistance of the regions while keeping a shallow junction position of the source and drain regions. However, fast metal diffusion during the silicide reaction easily penetrates the shallow junctions and induces leakage. To counter the leakage generation, source and drain regions could be elevated by selective epitaxial growth. Even with this elevation, the fast metal diffusion requires that a silicon layer must be selectively grown to a thickness almost equal to the height of a gate electrode. Unfortunately, however, it is very difficult to form such a thick film having a uniform thickness and quality with this method.
Thus, it is the object of the present invention to provide a semiconductor device that has a SALICIDE structure with low leakage currents and a source/drain height lower than the gate electrode, while maintaining shallow source and drain regions, without the above identified problems of conventional methods. It is also the object of the present invention to provide a method of manufacturing such a semiconductor device.